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| LSM320HAY30 MEMS motion sensor module: 3D digital accelerometer and 2D pitch and yaw analog gyroscope Features 2.7 V to 3.6 V power supply operation Low voltage compatible digital IOs, 1.8 V 2 g/4 g/8 g dynamically selectable full-scale 300 dps absolute analog angular rate output I2C/SPI digital linear acceleration interface (16 bit data output) Two separated outputs for pitch and yaw axis (1x and 4x amplified) Integrated low-pass filters for angular rate 2 independent programmable interrupt generators for free-fall and motion detection Sleep-to-wakeup function 6D orientation detection Extended operating temperature range (40 C to +85 C) High stability over temperature High shock survivability Embedded self-test Embedded power-down Embedded low-power mode ECOPACK(R) RoHS and "Green" compliant (see Section 9) LGA-28L (4.4x7.5x1.1mm) Description The LSM320HAY30 is a low-power system-inpackage featuring a 3D digital linear acceleration sensor and a 2D analog angular rate pitch and yaw sensor. It provides excellent temperature stability and high resolution over an extended operating temperature range (-40C to +85C). ST's family of sensor modules leverages the robust and mature manufacturing process already used for the production of micromachined accelerometers. The LSM320HAY30 has a dynamically user-selectable full-scale acceleration range of 2 g/4 g/8 g, and an angular rate of 300 dps capable of detecting rates with a -3 dB bandwidth up to 140 Hz along pitch and yaw axes. The LSM320HAY30 is capable of measuring linear accelerations with output data rates from 0.5 Hz up to 1 kHz. The embedded self-test capability allows the user to check the functioning of each sensor in the final application. The device can be configured to generate an interrupt signal by inertial wakeup/free-fall events as well as by the position of the device itself. Several years ago ST successfully pioneered the use of this package for accelerometers. Today, ST has the widest manufacturing capability and strongest expertise in the world for production of sensors in plastic LGA packages. Applications Motion control for smart user interface Display orientation Gaming and virtual reality input devices Industrial and robotics Vibration monitoring and compensation Impact recognition and logging Motion-activated functions Intelligent power-saving for handheld devices Free-fall detection December 2009 Doc ID 16917 Rev 1 1/42 www.st.com 42 Contents LSM320HAY30 Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 2.2 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Functionality and terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 4.2 4.3 4.4 4.5 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Zero level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Advanced features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5.1 4.5.2 Linear acceleration sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Angular rate sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 5.2 5.3 Linear acceleration sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Angular rate sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 6.2 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.1 6.2.2 6.2.3 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 8 2/42 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Doc ID 16917 Rev 1 LSM320HAY30 Contents 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 LA_CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 LA_CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 LA_CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 LA_CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 LA_CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 LA_HP_FILTER_RESET (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 REFERENCE (26h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ) 32 LA_STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 LA_OUT_X_L (28h), LA_OUT_X_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . 33 LA_OUT_Y_L (2Ah), LA_OUT_Y_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . 33 LA_OUT_Z_L (2Ch), LA_OUT_Z_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . 33 LA_INT1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 LA_INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 LA_INT1_THS (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 LA_INT1_DURATION (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 LA_INT2_CFG (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 LA_INT2_SRC (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 LA_INT2_THS (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 LA_INT2_DURATION (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 10 11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Doc ID 16917 Rev 1 3/42 List of tables LSM320HAY30 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Angular rate sleep mode and power-down mode configuration . . . . . . . . . . . . . . . . . . . . . 14 External component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 20 Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 20 Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 LA_CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 LA_CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Power mode and low-power output data rate configurations . . . . . . . . . . . . . . . . . . . . . . . 27 Normal mode output data rate configurations and low-pass cut-off frequencies . . . . . . . . 27 LA_CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 LA_CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 High-pass filter cut-off frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 LA_CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 LA_CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Data signal on INT 1 and INT 2 pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 LA_CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 LA_CTRL_REG4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 LA_CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 LA_CTRL_REG5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Sleep-to-wake configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 REFERENCE description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 LA_STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 LA_STATUS_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 LA_INT1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 LA_INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Interrupt 1 source configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 LA_INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 LA_INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 LA_INT1_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 LA_INT1_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 LA_INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 LA_INT2_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 LA_INT2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 LA_INT2_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Interrupt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 LA_INT2_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4/42 Doc ID 16917 Rev 1 LSM320HAY30 Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. List of tables LA_INT2_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 LA_INT2_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 LA_INT2_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 LA_INT2_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 LA_INT2_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Doc ID 16917 Rev 1 5/42 List of figures LSM320HAY30 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 LSM320HAY30 electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Angular rate output response vs. rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Multiple byte SPI read protocol (2 byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Multiple byte SPI write protocol (2 byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 LGA-28: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6/42 Doc ID 16917 Rev 1 LSM320HAY30 Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram Doc ID 16917 Rev 1 7/42 Block diagram and pin description LSM320HAY30 1.1 Pin connection and description Figure 2. Pin connection Table 1. Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Pin description Name Vdd_IO SCL/SPC CS SDA/SDI/SDO SDO/SA0 INT1 INT2 ARHP ARPD ARST GND GND RES GND GND FILTVDD VCONT OUT X Power supply for I/O pins I2C serial clock (SCL)/SPI serial port clock (SPC) SPI enable/I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) I2C serial data (SDA)/SPI serial data input (SDI) 3-wire interface serial data output (SDO) SPI serial data output (SDO)/ I2C less significant bit of the device address (SA0) Inertial interrupt 1 Inertial interrupt 2 Angular rate high-pass filter reset (logic 0: normal operation mode; logic1: external high-pass filter is reset) Angular rate power-down (see Table 5) Angular rate self-test (see Table 5) 0 V supply 0 V supply 0 V supply 0 V supply 0 V supply PLL filter connection pin 16 PLL filter connection pin 15 Not amplified Out X Function 8/42 Doc ID 16917 Rev 1 LSM320HAY30 Table 1. Pin# 19 20 21 22 23 24 25 26 27 28 Block diagram and pin description Pin description (continued) Name 4xIN X 4xOUT X Vref 4x OUTZ 4xIN Z OUT Z VDD RES RES RES Input of 4x amplifier X rate signal output voltage (amplified) Reference voltage Z rate signal output voltage (amplified) Input of 4x amplifier Not amplified Out Z Power supply Connected to Vdd Connected to Vdd Connected to Vdd Function Doc ID 16917 Rev 1 9/42 Mechanical and electrical specifications LSM320HAY30 2 2.1 Mechanical and electrical specifications Mechanical characteristics @ Vdd=3,0 V, T=25 C unless otherwise noted.(a) Table 2. Symbol (1) Mechanical characteristics Parameter Test conditions Min. Typ.(2) 2.0 4.0 8.0 300 1200 0.9 1.8 3.5 1 2 3.9 3.33 0.83 0.01 0.07 20 0.1 1.5 1.5 Max delta from 25C FS bit set to 00 0.05 218 0.02 Best fit straight line 1 ODR/2 140 FS bit set to 00 X axis +500 -500 +600 1.1 2.2 4.3 mV/dps mV/dps %/C %/C mg mg/C V V dps/C g/Hz dps/Hz % FS Hz Hz LSb LSb LSb mg/digit dps g Max. Unit LA_FS FS bit set to 00 Linear acceleration measurement FS bit set to 01 range(3) FS bit set to 11 Angular rate measurement range 4x OUT (amplified) OUT (not amplified) FS bit set to 00 (12 bit) AR_FS LA_So Linear acceleration sensitivity FS bit set to 01 (12 bit) FS bit set to 11 (12 bit) AR_So LA_TCSo AR_TCSo LA_TyOff LA_TCOff AR_Zrl AR_Vref AR_TCZrl LA_An AR_Rn AR_NL LA_BW AR_BW Angular rate sensitivity(4) Linear acceleration sensitivity change vs. temperature 4x OUT (amplified) OUT (not amplified) FS bit set to 00 Angular rate sensitivity change vs Delta from 25C temperature Linear acceleration typical zero-g level offset accuracy(5),(6) Linear acceleration zero-g level change vs. temperature Zero-rate level(6) Reference voltage Angular rate zero-rate level change vs. temperature Linear acceleration noise density Angular rate noise density Angular rate non linearity Linear acceleration Angular rate bandwidth(7) bandwidth(8) FS bit set to 00 Max delta from 25C LA_ST Linear acceleration self-test output change(9),(10),(11) FS bit set to 00 Y axis FS bit set to 00 Z axis a. The product is factory calibrated at 3.0 V. The operational power supply range is from 2.7 V to 3.6 V. 10/42 Doc ID 16917 Rev 1 LSM320HAY30 Table 2. Symbol(1) AR_ST Top Mechanical and electrical specifications Mechanical characteristics (continued) Parameter Angular rate self-test output change Operating temperature range -40 Test conditions Min. Typ.(2) 250 +85 Max. Unit mV C 1. Linear acceleration (LA), Angular Rate (AR) parameter labeling 2. Typical specifications are not guaranteed 3. Verified by wafer level test and measurement of initial offset and sensitivity 4. Sensitivity and zero-rate offset are not ratiometric to supply voltage 5. Typical zero-g level offset value after MSL3 preconditioning 6. Offset can be eliminated by enabling the built-in high-pass filter 7. Refer to Table 23 for filter cut-off frequency. 8. The product is capable of measuring angular rates extending from DC to the selected BW. 9. The sign of "Self-test output change" is defined by LA_CTRL_REG4 STsign bit (Table 27), for all axes. 10. Linear acceleration sensing Self-Test output changes with the power supply. "Self-test output change" is defined as OUTPUT[LSb](LA_CTRL_REG4 ST bit=1) - OUTPUT[LSb](LA_CTRL_REG4 ST bit=0). 1LSb=4g/4096 at 12bit representation, 2 g Full-scale 11. Output data reach 99% of final value after 1/ODR+1ms when enabling linear acceleration sensing self-test mode, due to device filtering. 2.2 Electrical characteristics @ Vdd=3,0 V, T=25 C unless otherwise noted.(b) Table 3. Symbol Vdd Vdd_IO LA_Idd AR_Idd LA_IddLP AR_IddSl LA_IddPdn AR_IddPdn Electrical characteristics Parameter Supply voltage I/O pins supply voltage(2) ODR = 50 Hz ARPD pin connected to GND ODRLP = 0.5 Hz ARPD, ARST pin connected to Vdd Test condition Min. 2.7 1.71 0.25 6.8 10 2.1 1 ARPD pin connected to Vdd 1 5 5 Typ.(1) 3.0 Max. 3.6 Vdd+0.1 Unit V V mA mA A mA A A Linear acceleration current consumption in normal mode Angular rate current consumption in normal mode Linear acceleration current consumption in low-power mode Angular rate current consumption in sleep mode Linear acceleration current consumption in power-down mode Angular rate current consumption in power-down mode b. The product is factory calibrated at 3 V. Doc ID 16917 Rev 1 11/42 Mechanical and electrical specifications Table 3. Symbol AR_VST LSM320HAY30 Electrical characteristics (continued) Parameter Angular rate self-test input Logic 1 level Logic 0 level 0.8*Vdd 0 0.8*Vdd 0.8*Vdd_IO 0.2*Vdd_IO 0.9*Vdd_IO 0.1*Vdd_IO DR bit set to 00 50 100 Hz DR bit set to 10 DR bit set to 11 PM bit set to 010 PM bit set to 011 400 1000 0.5 1 2 5 10 1/ODR+1 ms 200 -40 +85 s ms Hz Vdd 0.2*Vdd V Logic 1 level Vdd V V V V Test condition Logic 0 level Min. 0 Typ.(1) Max. 0.2*Vdd V Unit AR_VPD Angular rate power-down input Linear acceleration digital high level input voltage Linear acceleration digital low level input voltage Linear acceleration high level output voltage Linear acceleration low level output voltage LA_VIH LA_VIL LA_VOH LA_VOL LA_ODR Linear acceleration output data rate in normal mode DR bit set to 01 Linear acceleration output data LA_ODRLP rate in low-power mode PM bit set to 100 PM bit set to 101 PM bit set to 110 LA_Ton AR_Ton Top Linear acceleration turn-on time(3) ODR = 100 Hz Angular rate turn-on time(4) Operating temperature range C 1. Typical specifications are not guaranteed 2. It is possible to remove Vdd, maintaining Vdd_IO without blocking the communication buses. In this condition the measurement chain is powered off. 3. Time to obtain valid data after exiting power-down mode 4. Time to obtain valid data after exiting power-down mode 12/42 Doc ID 16917 Rev 1 LSM320HAY30 Absolute maximum ratings 3 Absolute maximum ratings Stresses above those listed as "Absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 4. Symbol Vdd Vin A Vdd_IO Vin Supply voltage Input voltage on any control pin (PD, ST) Acceleration 10000 for 0.1 ms I/O pin supply voltage Input voltage on any control pin (CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0) Acceleration (any axis, powered, Vdd = 3 V) 10000 for 0.1 ms 3000 for 0.5 ms AUNP TOP TSTG ESD Acceleration (any axis, unpowered) 10000 for 0.1 ms Operating temperature range Storage temperature range Electrostatic discharge protection -40 to +85 -40 to +125 2 (HBM) -0.3 to 6 -0.3 to Vdd_IO +0.3 3000 for 0.5 ms APOW Absolute maximum ratings Ratings Maximum value -0.3 to 4.8 -0.3 to Vdd +0.3 3000 for 0.5 ms Unit V V g g V V g g g g C C kV This is a mechanical shock sensitive device, improper handling can cause permanent damage to the part. This is an ESD sensitive device, improper handling can cause permanent damage to the part. Doc ID 16917 Rev 1 13/42 Functionality and terminology LSM320HAY30 4 Functionality and terminology The LSM320HAY30 is an inertial module capable of detecting 3-axis linear acceleration and 2-axis angular rate. The system is housed in an LGA package. The device includes an ASIC with a digital IC interface capable of providing linear acceleration information through an I2C/SPI serial interface and analog output related to angular rate. The LSM320HAY30 may also be configured to generate an inertial wakeup and free-fall interrupt signal according to a programmed acceleration event along the enabled axes. Both free-fall and wakeup can be used simultaneously on two different pins (INT1/INT2). 4.1 Factory calibration The system is factory calibrated for sensitivity and zero level. The trimming values are stored inside the device in non-volatile memory. When the device is turned on, the trimming parameters are downloaded into the registers to be used during active operation. This allows the use of the device without further calibration. 4.2 Sensitivity Linear acceleration sensing Liner Acceleration Sensitivity (LA_So) describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, a 1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large number of sensors. Angular rate sensing Angular rate detection produces a positive-going output voltage for counter-clockwise rotation around the sensitive axis considered. Angular Rate Sensitivity (AR_So) describes the gain of the sensor and can be determined by applying a defined angular rate to it. This value changes very little over temperature and over time. 4.3 Zero level Zero-g level Zero-g level Offset (LA_TyOff) describes the deviation of an actual output signal from the ideal output signal if no linear acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on both the X and Y axes, whereas the Z axis will measure 1 g. Ideally, the output is in the middle of the dynamic range of the sensor (content 14/42 Doc ID 16917 Rev 1 LSM320HAY30 Functionality and terminology of OUT registers 00h, data expressed as 2's complement number). A deviation from the ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Zero-g level offset changes little over temperature, see "Zero-g level change vs. temperature" (LA_TCOff) in Table 2. The Zero-g level tolerance (LA_TyOff) describes the standard deviation of the range of Zero-g levels of a group of sensors. Zero-rate level Angular rate zero-rate level (AR_Zrl) describes the actual angular rate output signal if there is no angular rate present. Zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and therefore zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and time. 4.4 Self-test Linear acceleration self-test Self-test allows the checking of sensor functionality without moving it. The self-test function is off when the self-test bit (ST) of LA_CTRL_REG4 (control register 4) is programmed to `0`. When the self-test bit of LA_CTRL_REG4 is programmed to `1` an actuation force is applied to the sensor, simulating a definite input acceleration. In this case, the sensor outputs will exhibit a change in their DC levels which are related to the selected full-scale through the device sensitivity. When self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified in Table 2, then the sensor is working properly and the parameters of the interface chip are within the defined specifications. Angular rate self-test Self-test allows testing of the mechanical and electric parts of the sensor, permitting the seismic mass to be moved by means of an electrostatic test-force. The self-test function is off when the ARST pin is connected to GND. When the ARST pin is tied to Vdd and ARPD is tied to GND (see Table 5), an actuation force is applied to the sensor, emulating a definite Coriolis force. In this case the sensor output exhibits a voltage change in its DC level which is also dependent on the supply voltage. When ST is active, the device output level is given by the algebraic sum of the signals produced by the velocity acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified in Table 2, then the mechanical element is working properly and the parameters of the interface chip are within the defined specifications. Doc ID 16917 Rev 1 15/42 Functionality and terminology LSM320HAY30 4.5 4.5.1 Advanced features Linear acceleration sensing The LSM320HAY30 linear acceleration sensor includes a low-power mode characterized by lower data rate refreshing. In this way the device, even when sleeping, continues sensing acceleration and generating interrupt requests. The "sleep-to-wakeup" function, in conjunction with low-power mode, allows further reduction of system power consumption and the development of new smart applications. When the sleep-to-wakeup function is activated,the LSM320HAY30 is able to automatically wake up the linear acceleration sensor as soon as an interrupt event has been detected. With this feature the system is efficiently switched from low-power mode to normal mode based on user-selectable positioning and acceleration events, thus ensuring power-saving and flexibility. 4.5.2 Angular rate sensing Sleep mode, self-test and power-down The LSM320HAY30 has advanced power-saving features for angular rate sensing thanks to the availability of three different operating modes. When the device is set to sleep mode configuration, the reading chain is completely turned off, resuting in low power consumption. In this condition, the device turn-on time is significantly reduced, allowing simple external power cycling. Based on the table below, the user can select the desired operating mode using two dedicated pins (ARST and ARPD). Table 5. Angular rate sleep mode and power-down mode configuration ARST pin 0 0 1 1 ARPD pin 0 1 0 1 Operating mode Normal mode Power-down Self-test Sleep mode High-pass filter reset (ARHP) The LSM320HAY30 provides the possibility to reset the optional external high-pass filter by applying a high logic value to the ARHP pad. This procedure ensures faster response, especially during overload conditions. Moreover, this operation is recommended each time the device is powered. 16/42 Doc ID 16917 Rev 1 LSM320HAY30 Application hints 5 Application hints Figure 3. LSM320HAY30 electrical connections Z Z 1 Y + z 1 Y DIRECTION OF DETECTABLE ACCELERATIONS X DIRECTION OF DETECTABLE ANGULAR RATE X + x Vdd_IO Vdd SDO/SA0 SDA/SDI/SDO SCL/SPC ARPD ARST ARHP INT2 INT1 CS C6 C5 28 RES RES RES 25 VDD 10 GND GND GND RES 14 15 FILTVDD GND OUT X R2 C1 C2 GND Recommended Low-pass filter 1 11 LSM320HAY30 (TOP VIEW) FILTVDD F FILTIN Y 4xOUTX VCONT VREF C3 C4 R3 24 4xOUTY OUT Z C1 4xIN Z R1 C2 GND Optional High-pass filter R2 R1 Vref Optional High-pass filter 4xIN X Vref Recommended Low-pass filter Digital signal from/to signal controller.Signal's levels are defined by proper selection of Vdd_IO AM06041v1 Table 6. External component values Component C1 C2 C3 Capacitor C4 C5 C6 R1 Resistor R2 R3 10 nF 100 nF 10 F 1 M 33 k 10 k Value 4.7 F 2.2 nF to 2.2 F 470 nF Component type Doc ID 16917 Rev 1 17/42 Application hints LSM320HAY30 The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1=100 nF ceramic, C2=10 F aluminum) should be placed as near as possible to the supply pin of the device (common design practice). All voltage and ground supplies must be present at the same time to obtain proper behavior of the IC (refer to Figure 3). 5.1 Linear acceleration sensing The functionality of the device and the measured acceleration data is selectable and accessible through the SPI/I2C interface. The functions, the threshold and the timing of the two interrupt pins (INT 1 and INT 2) can be completely programmed by the user though the SPI/I2C interface. 5.2 Angular rate sensing The LSM320HAY30 allows band limitation of the output rate response through the use of an external low-pass filter (recommended) and/or high-pass filter (optional) in addition to the embedded low-pass filter (ft = 140 Hz). 4xOUTX and 4xOUTZ are, respectively, OUTX and OUTZ amplified outputs lines, internally buffered to ensure low output impedance. If external filtering is not applied, it is mandatory to short-circuit pad 18 to pad 19 and pad 23 to pad 24, respectively, when amplified outputs are used. When only a non-amplified output is used (OUTX/OUTZ), it is recommended to set pin 19 and 23 to a fixed reference voltage (Vref). The LSM320HAY30 IC includes a PLL (phase locked loop) circuit to synchronize driving and sensing interfaces. Capacitors and resistors must be added at the FILTVDD and VCONT pins (as shown in Figure 3) to implement a second-order low-pass filter. Figure 4. Z 1 Angular rate output response vs. rotation Z + z 1 Y X + x Steady state position: 4xOUTX = 4xOUTZ = 1.5V OUTX = OUTZ = 1.5V Positive rotations as indicated by the arrows increase output value over Zero rate level: +300/sec --> 4xOUTX, 4xOUTZ = 1.5V + SoA*300 = 2.5V +300/sec --> OUTX, OUTZ = 1.5V + So*300 = 1.75V AM06042v1 18/42 Doc ID 16917 Rev 1 LSM320HAY30 Application hints 5.3 Soldering information The LGA package is compliant with the ECOPACK(R), RoHS and "Green" standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Leave "pin 1 Indicator" unconnected during soldering. Land pattern and soldering recommendations are available at www.st.com. Doc ID 16917 Rev 1 19/42 Digital interfaces LSM320HAY30 6 Digital interfaces The registers embedded in the LSM320HAY30 may be accessed through both the I2C and SPI serial interfaces. The latter may be software configured to operate either in 3-wire or 4wire interface mode. The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, the CS line must be tied high (i.e. connected to Vdd_IO). Table 7. Serial interface pin description Pin description SPI enable I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) I2C serial clock (SCL) SPI serial port clock (SPC) I2C serial data (SDA) SPI serial data input (SDI) 3-wire interface serial data output (SDO) I2C less significant bit of the device address (SA0) SPI serial data output (SDO) Pin name CS SCL SPC SDA SDI SDO SA0 SDO 6.1 I2C serial interface The LSM320HAY30 I2C is a bus slave. The I2C is employed to write data into registers whose content can also be read back. The relevant I2C terminology is given in the table below. Table 8. Term Transmitter Receiver Master Slave Serial interface pin description Description The device which sends data to the bus The device which receives data from the bus The device which initiates a transfer, generates clock signals and terminates a transfer The device addressed by the master There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor embedded inside the LSM320HAY30. When the bus is free, both the lines are high. The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with normal mode. 20/42 Doc ID 16917 Rev 1 LSM320HAY30 Digital interfaces 6.1.1 I2C operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a high to low transition on the data line while the SCL line is held high. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the 8th bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master. The Slave ADdress (SAD) associated with the LSM320HAY30 is 001100xb. The SDO/SA0 pad can be used to modify the least significant bit of the device address. If the SA0 pad is connected to voltage supply, LSb is `1' (address 0011001b), otherwise if the SA0 pad is connected to ground, the LSb value is `0' (address 0011000b). This solution permits connecting and addressing two different accelerometers to the same I2C lines. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. The I2C embedded in the LSM320HAY30 behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent. Once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the 7 LSb represent the actual register address while the MSB enables address auto-increment. If the MSb of the SUB field is `1', the SUB (register address) is automatically incremented to allow multiple data read/write. The slave address is completed with a read/write bit. If the bit was `1' (read), a repeated START (SR) condition will have to be issued after the two sub-address bytes; if the bit is `0' (write) the master transmits to the slave with direction unchanged. Table 9 explains how the SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 9. SAD+Read/Write patterns SAD[6:1] 001100 001100 001100 001100 SAD[0] = SA0 0 0 1 1 R/W 1 0 1 0 SAD+R/W 00110001 (31h) 00110000 (30h) 00110011 (33h) 00110010 (32h) Command Read Write Read Write Table 10. Master Slave Transfer when master is writing one byte to slave ST SAD + W SAK SUB SAK DATA SAK SP Doc ID 16917 Rev 1 21/42 Digital interfaces LSM320HAY30 Table 11. Master Slave Transfer when master is writing multiple bytes to slave ST SAD + W SAK SUB SAK DATA SAK DATA SAK SP Table 12. Master Slave ST Transfer when master is receiving (reading) one byte of data from slave SAD + W SAK SUB SAK SR SAD + R SAK DATA NMAK SP Table 13. Master Slave Transfer when master is receiving (reading) multiple bytes of data from slave ST SAD+W SAK SUB SAK SR SAD+R SAK DATA MAK DATA MAK DATA NMAK SP Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit (MSb) first. If a receiver cannot receive another complete byte of data until it has performed some other function, it can hold the clock line SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to receive because it is performing a real-time function) the data line must be left HIGH by the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of the first register to be read. In the presented communication format MAK is Master Acknowledge and NMAK is No Master Acknowledge. 6.2 SPI bus interface The LSM320HAY30 SPI is a bus slave. The SPI allows writing and reading of the registers of the device. The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. 22/42 Doc ID 16917 Rev 1 LSM320HAY30 Figure 5. CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 Digital interfaces Read and write protocol DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CS is the serial port enable and is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the serial port data input and output. These lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple bytes read/write. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS. bit 0: RW bit. When 0, the data DI(7:0) is written to the device. When 1, the data DO(7:0) from the device is read. In the latter case, the chip drives SDO at the start of bit 8. bit 1: MS bit. When 0, the address remains unchanged in multiple read/write commands. When 1, the address is auto incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). In multiple read/write commands, further blocks of 8 clock periods are added. When the MS bit is `0' the address used to read/write data remains the same for every block. When the MS bit is `1' the address used to read/write data is incremented at every block. The function and the behavior of SDI and SDO remain unchanged. 6.2.1 SPI read Figure 6. SPI read protocol CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Doc ID 16917 Rev 1 23/42 Digital interfaces LSM320HAY30 The SPI Read command is performed with 16 clock pulses. A multiple byte read command is performed adding blocks of 8 clock pulses after the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When 0, do not increment the address. When 1, increment the address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). bit 16-... : data DO(...-8). Further data in multiple byte reading. Figure 7. CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 Multiple byte SPI read protocol (2 byte example) SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 6.2.2 SPI write Figure 8. CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SPI write protocol The SPI Write command is performed with 16 clock pulses. A multiple byte write command is performed adding blocks of 8 clock pulses after the previous one. bit 0: WRITE bit. The value is 0. bit 1: MS bit. When 0, do not increment the address. When 1, increment the address in multiple writing. bit 2 -7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written to the device (MSb first). bit 16-... : data DI(...-8). Further data in multiple byte writing. 24/42 Doc ID 16917 Rev 1 LSM320HAY30 Figure 9. CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 Digital interfaces Multiple byte SPI write protocol (2 byte example) DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 6.2.3 SPI read in 3-wires mode 3-wires mode is entered by setting to `1' bit SIM (SPI serial interface mode selection) in LA_CTRL_REG4. Figure 10. SPI read protocol in 3-wires mode CS SPC SDI/O RW MS AD5 AD4 AD3 AD2 AD1 AD0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 The SPI Read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1: MS bit. When 0, do not increment the address. When 1, increment the address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). Multiple read command is also available in 3-wires mode. Doc ID 16917 Rev 1 25/42 Register mapping LSM320HAY30 7 Register mapping The table given below provides a listing of the 8-bit registers embedded in the device and the related addresses: Table 14. Register address map Register address Name Reserved (do not modify) WHO_AM_I Reserved (do not modify) LA_CTRL_REG1 LA_CTRL_REG2 LA_CTRL_REG3 LA_CTRL_REG4 LA_CTRL_REG5 LA_HP_FILTER_RESET LA_REFERENCE LA_STATUS_REG LA_OUT_X_L LA_OUT_X_H LA_OUT_Y_L LA_OUT_Y_H LA_OUT_Z_L LA_OUT_Z_H Reserved (do not modify) LA_INT1_CFG LA_INT1_SOURCE LA_INT1_THS LA_INT1_DURATION LA_INT2_CFG LA_INT2_SOURCE LA_INT2_THS LA_INT2_DURATION Reserved (do not modify) rw r rw rw rw r rw rw rw rw rw rw rw r rw r r r r r r r r Type Hex 00 - 0E 0F 10 - 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E - 2F 30 31 32 33 34 35 36 37 38 - 3F 011 0000 00000000 011 0001 00000000 011 0010 00000000 011 0011 00000000 011 0100 00000000 011 0101 00000000 011 0110 00000000 011 0111 00000000 Reserved 010 0000 00000111 010 0001 00000000 010 0010 00000000 010 0011 00000000 010 0100 00000000 010 0101 010 0110 00000000 010 0111 00000000 010 1000 010 1001 010 1010 010 1011 010 1100 010 1101 output output output output output output Reserved Dummy register 000 1111 00110010 Binary Reserved Dummy register Reserved Default Comment 26/42 Doc ID 16917 Rev 1 LSM320HAY30 Register mapping Registers marked as Reserved must not be changed. Writing to these registers may cause permanent damage to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibrated values. Their content is automatically restored when the device is powered up. Doc ID 16917 Rev 1 27/42 Register description LSM320HAY30 8 Register description The device contains a set of registers which are used to control acceleration portion behavior and to retrieve acceleration data. The register address, composed of 7 bits, is used to identify them and to write the data through the serial interface. 8.1 WHO_AM_I (0Fh) Table 15. 0 WHO_AM_I register 0 1 1 0 0 1 0 This register is the device identification register, and contains the device identifier which, for the LSM320HAY30, is set to 32h. 8.2 LA_CTRL_REG1 (20h) Table 16. PM2 LA_CTRL_REG1 register PM1 PM0 DR1 DR0 Zen Yen Xen Table 17. PM2 - PM0 DR1, DR0 Zen Yen Xen LA_CTRL_REG1 description Power mode selection. Default value: 000 (000: Power-down; Others: refer to Table 18) Data rate selection. Default value: 00 (00:50 Hz; others: refer to Table 19) Z axis enable. Default value: 1 (0: Z axis disabled; 1: Z axis enabled) Y axis enable. Default value: 1 (0: Y axis disabled; 1: Y axis enabled) X axis enable. Default value: 1 (0: X axis disabled; 1: X axis enabled) PM bits allow selection between power-down and two operating active modes. The device is in power-down mode when the PD bits are set to "000" (default value after boot). Table 18 shows all the possible power mode configurations and respective output data rates. Output data in the low-power modes are computed with a low-pass filter cut-off frequency defined by DR1, DR0 bits. DR bits, in normal mode operation, select the data rate at which acceleration samples are produced. In low-power mode they define the output data resolution. Table 19 shows all the possible configurations for the DR1 and DR0 bits. 28/42 Doc ID 16917 Rev 1 LSM320HAY30 Register description Table 18. PM2 0 0 0 0 1 1 1 Power mode and low-power output data rate configurations PM1 0 0 1 1 0 0 1 PM0 0 1 0 1 0 1 0 Power mode selection Power-down Normal mode Low power Low power Low power Low power Low power Output data rate [Hz] ODRLP -ODR 0.5 1 2 5 10 Table 19. Normal mode output data rate configurations and low-pass cut-off frequencies DR0 0 1 0 1 Output data rate [Hz] ODR 50 100 400 1000 Low-pass filter cut-off frequency [Hz] 37 74 292 780 DR1 0 0 1 1 8.3 LA_CTRL_REG2 (21h) Table 20. BOOT LA_CTRL_REG2 register HPM1 HPM0 FDS HPen2 HPen1 HPCF1 HPCF0 Table 21. BOOT LA_CTRL_REG2 description Reboot memory content. Default value: 0 (0: normal mode; 1: reboot memory content) High-pass filter mode selection. Default value: 00 (00: normal mode. Others: refer to Table 22) Filtered data selection. Default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register) High-pass filter enabled for Interrupt 2 source. Default value: 0 (0: filter bypassed; 1: filter enabled) HPM1, HPM0 FDS HPen2 Doc ID 16917 Rev 1 29/42 Register description Table 21. HPen1 HPCF1, HPCF0 LSM320HAY30 LA_CTRL_REG2 description (continued) High-pass filter enabled for Interrupt 1 source. Default value: 0 (0: filter bypassed; 1: filter enabled) High-pass filter cut-off frequency configuration. Default value: 00 (00: HPc=8; 01: HPc=16; 10: HPc=32; 11: HPc=64) The BOOT bit is used to refresh the content of the internal registers stored in the Flash memory block. At device power-up, the content of the Flash memory block is transferred to the internal registers related to trimming functions to permit good device behavior. If, for any reason, the content of the trimming registers was changed, it is sufficient to use this bit to restore the correct values. When the BOOT bit is set to `1', the content of internal Flash is copied to the corresponding internal registers and is used to calibrate the device. These values are factory-trimmed and are different for every accelerometer. They permit good device behavior and normally do not have to be modified. At the end of the boot process, the BOOT bit is again set to `0'. Table 22. HPM1 0 0 1 High-pass filter mode configuration HPM0 0 1 0 High-pass filter mode Normal mode (reset reading HP_RESET_FILTER) Reference signal for filtering Normal mode (reset reading HP_RESET_FILTER) HPCF[1:0]. These bits are used to configure the high-pass filter cut-off frequency ft which is given by: fs 1f t = ln 1 - ----------- ----- HPc 2 The equation can be simplified to the following approximated equation: fs f t = --------------------6 HPc Table 23. HPcoeff2,1 00 01 10 11 High-pass filter cut-off frequency configuration ft [Hz] Data rate = 50 Hz 1 0.5 0.25 0.125 ft [Hz] Data rate = 100 Hz 2 1 0.5 0.25 ft [Hz] ft [Hz] Data rate = 400 Hz Data rate = 1000 Hz 8 4 2 1 20 10 5 2.5 30/42 Doc ID 16917 Rev 1 LSM320HAY30 Register description 8.4 LA_CTRL_REG3 (22h) Table 24. IHL LA_CTRL_REG3 register PP_OD LIR2 I2_CFG1 I2_CFG0 LIR1 I1_CFG1 I1_CFG0 Table 25. IHL PP_OD LA_CTRL_REG3 description Interrupt active high, low. Default value: 0 (0: active high; 1: active low) Push-pull/open drain selection on interrupt pad. Default value 0. (0: push-pull; 1: open drain) Latch interrupt request on INT2_SRC register, with INT2_SRC register cleared by reading INT2_SRC itself. Default value: 0. (0: interrupt request not latched; 1: interrupt request latched) Data signal on INT 2 pad control bits. Default value: 00. (see table below) Latch interrupt request on INT1_SRC register, with INT1_SRC register cleared by reading INT1_SRC register. Default value: 0. (0: interrupt request not latched; 1: interrupt request latched) Data signal on INT 1 pad control bits. Default value: 00. (see table below) LIR2 I2_CFG1, I2_CFG0 LIR1 I1_CFG1, I1_CFG0 Table 26. Data signal on INT 1 and INT 2 pad I1(2)_CFG0 0 1 0 1 INT 1(2) Pad Interrupt 1 (2) source Interrupt 1 source OR Interrupt 2 source Data ready Boot running I1(2)_CFG1 0 0 1 1 8.5 LA_CTRL_REG4 (23h) Table 27. BDU LA_CTRL_REG4 register BLE FS1 FS0 STsign 0 ST SIM Doc ID 16917 Rev 1 31/42 Register description LSM320HAY30 Table 28. BDU LA_CTRL_REG4 description Block data update. Default value: 0 (0: continuous update; 1: output registers not updated between MSB and LSB reading) Big/little endian data selection. Default value 0. (0: data LSB @ lower address; 1: data MSB @ lower address) Full-scale selection. Default value: 00. (00: 2 g; 01: 4 g; 11: 8 g) Self-test sign. Default value: 00. (0: self-test plus; 1 self-test minus) Self-test enable. Default value: 0. (0: self-test disabled; 1: self-test enabled) SPI serial interface mode selection. Default value: 0. (0: 4-wire interface; 1: 3-wire interface) BLE FS1, FS0 STsign ST SIM The BDU bit is used to inhibit output register updates between the reading of the upper and lower register parts. In default mode (BDU = `0'), the lower and upper register parts are updated continuously. If it is not certain to read faster than the output data rate, it is recommended to set BDU bit to `1'. In this way, after the reading of the lower (upper) register part, the content of that output register is not updated until the upper (lower) part is read also. This feature avoids reading LSB and MSB related to different samples. 8.6 LA_CTRL_REG5 (24h) Table 29. 0 LA_CTRL_REG5 register 0 0 0 0 0 TurnOn1 TurnOn0 Table 30. TurnOn1, TurnOn0 LA_CTRL_REG5 description Turn-on mode selection for sleep-to-wake function. Default value: 00. TurnOn bits are used for turning on the sleep-to-wake function. Table 31. TurnOn1 0 1 Sleep-to-wake configuration TurnOn0 0 1 Sleep-to-wake status Sleep-to-wake function is disabled Turned on: The device is in low-power mode (ODR is defined in LA_CTRL_REG1) 32/42 Doc ID 16917 Rev 1 LSM320HAY30 Register description By setting the TurnOn[1:0] bits to 11, the "sleep-to-wake" function is enabled. When an interrupt event occurs, the device is goes into normal mode, increasing the ODR to the value defined in LA_CTRL_REG1. Although the device is in normal mode, LA_CTRL_REG1 content is not automatically changed to "normal mode" configuration. 8.7 LA_HP_FILTER_RESET (25h) Dummy register. Reading at this address instantaneously zeroes the content of the internal high-pass filter. If the high-pass filter is enabled, all three axes are instantaneously set to 0 g. This makes it possible to surmount the settling time of the high-pass filter. 8.8 REFERENCE (26h) Table 32. Ref7 REFERENCE register Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0 Table 33. Ref7 - Ref0 REFERENCE description Reference value for high-pass filter. Default value: 00h. This register sets the acceleration value taken as a reference for the high-pass filter output. When the filter is turned on (at least one FDS, HPen2, or HPen1 bit is equal to `1') and HPM bits are set to "01", filter out is generated taking this value as a reference. 8.9 LA_STATUS_REG (27h) Table 34. ZYXOR LA_STATUS_REG register ZOR YOR XOR ZYXDA ZDA YDA XDA Table 35. ZYXOR LA_STATUS_REG description X, Y and Z axis data overrun. Default value: 0 (0: no overrun has occurred; 1: new data has overwritten the previous one before it was read) Z axis data overrun. Default value: 0 (0: no overrun has occurred; 1: new data for the Z-axis has overwritten the previous one) Y axis data overrun. Default value: 0 (0: no overrun has occurred; 1: new data for the Y-axis has overwritten the previous one) ZOR YOR Doc ID 16917 Rev 1 33/42 Register description Table 35. XOR ZYXDA ZDA LSM320HAY30 LA_STATUS_REG description (continued) X axis data overrun. Default value: 0 (0: no overrun has occurred; 1: new data for the X-axis has overwritten the previous one) X, Y and Z axis new data available. Default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) Z axis new data available. Default value: 0 (0: new data for the Z-axis is not yet available; 1: new data for the Z-axis is available) Y axis new data available. Default value: 0 (0: new data for the Y-axis is not yet available; 1: new data for the Y-axis is available) X axis new data available. Default value: 0 (0: new data for the X-axis is not yet available; 1: new data for the X-axis is available) YDA XDA 8.10 LA_OUT_X_L (28h), LA_OUT_X_H (29h) X-axis acceleration data. The value is expressed as two's complement. 8.11 LA_OUT_Y_L (2Ah), LA_OUT_Y_H (2Bh) Y-axis acceleration data. The value is expressed as two's complement. 8.12 LA_OUT_Z_L (2Ch), LA_OUT_Z_H (2Dh) Z-axis acceleration data. The value is expressed as two's complement. 8.13 LA_INT1_CFG (30h) Table 36. AOI LA_INT1_CFG register 6D ZHIE ZLIE YHIE YLIE XHIE XLIE Table 37. AOI 6D LA_INT1_CFG description AND/OR combination of interrupt events. Default value: 0. (See Table 38) 6 direction detection function enable. Default value: 0. (See Table 38) Enable interrupt generation on Z high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ZHIE 34/42 Doc ID 16917 Rev 1 LSM320HAY30 Table 37. ZLIE Register description LA_INT1_CFG description (continued) Enable interrupt generation on Z Low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X Low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) YHIE YLIE XHIE XLIE Configuration register for Interrupt 1 source. Table 38. AOI 0 0 1 1 Interrupt 1 source configurations 6D 0 1 0 1 Interrupt mode OR combination of interrupt events 6 direction movement recognition AND combination of interrupt events 6 direction position recognition 8.14 LA_INT1_SRC (31h) Table 39. 0 LA_INT1_SRC register IA ZH ZL YH YL XH XL Table 40. IA ZH ZL YH LA_INT1_SRC description Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) Z High. Default value: 0 (0: no interrupt, 1: Z high event has occurred) Z Low. Default value: 0 (0: no interrupt; 1: Z low event has occurred) Y High. Default value: 0 (0: no interrupt, 1: Y high event has occurred) Doc ID 16917 Rev 1 35/42 Register description Table 40. YL XH XL LSM320HAY30 LA_INT1_SRC description (continued) Y Low. Default value: 0 (0: no interrupt, 1: Y low event has occurred) X High. Default value: 0 (0: no interrupt, 1: X High event has occurred) X Low. Default value: 0 (0: no interrupt, 1: X Low event has occurred) Interrupt 1 source register. Read-only register. Reading at this address clears LA_INT1_SRC IA bit (and the interrupt signal on INT 1 pin) and allows the refreshing of data in the LA_INT1_SRC register if the latched option was chosen. 8.15 LA_INT1_THS (32h) Table 41. 0 LA_INT1_THS register THS6 THS5 THS4 THS3 THS2 THS1 THS0 Table 42. LA_INT1_THS description Interrupt 1 threshold. Default value: 000 0000 THS6 - THS0 8.16 LA_INT1_DURATION (33h) Table 43. 0 LA_INT1_DURATION register D6 D5 D4 D3 D2 D1 D0 Table 44. D6 - D0 LA_INT2_DURATION description Duration value. Default value: 000 0000 The D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized. Duration steps and maximum values depend on the ODR chosen. 8.17 LA_INT2_CFG (34h) Table 45. AOI LA_INT2_CFG register 6D ZHIE ZLIE YHIE YLIE XHIE XLIE 36/42 Doc ID 16917 Rev 1 LSM320HAY30 Register description Table 46. AOI 6D LA_INT2_CFG description AND/OR combination of Interrupt events. Default value: 0. (See table below) 6 direction detection function enable. Default value: 0. (See table below) Enable interrupt generation on Z High event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Z Low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on Y High event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y Low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on X High event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X Low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) ZHIE ZLIE YHIE YLIE XHIE XLIE Configuration register for Interrupt 2 source. Table 47. AOI 0 0 1 1 Interrupt mode configuration 6D 0 1 0 1 Interrupt mode OR combination of interrupt events 6 direction movement recognition AND combination of interrupt events 6 direction position recognition 8.18 LA_INT2_SRC (35h) Table 48. 0 LA_INT2_SRC register IA ZH ZL YH YL XH XL Doc ID 16917 Rev 1 37/42 Register description LSM320HAY30 Table 49. IA ZH ZL YH YL XH XL LA_INT2_SRC description Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) Z High. Default value: 0 (0: no interrupt, 1: Z High event has occurred) Z Low. Default value: 0 (0: no interrupt; 1: Z Low event has occurred) Y High. Default value: 0 (0: no interrupt, 1: Y High event has occurred) Y Low. Default value: 0 (0: no interrupt, 1: Y Low event has occurred) X High. Default value: 0 (0: no interrupt, 1: X High event has occurred) X Low. Default value: 0 (0: no interrupt, 1: X Low event has occurred) Interrupt 2 source register. Read-only register. Reading at this address clears the LA_INT2_SRC IA bit (and the interrupt signal on INT 2 pin) and allows the refreshing of data in the LA_INT2_SRC register if the latched option was chosen. 8.19 LA_INT2_THS (36h) Table 50. 0 LA_INT2_THS register THS6 THS5 THS4 THS3 THS2 THS1 THS0 Table 51. LA_INT2_THS description Interrupt 1 threshold. Default value: 000 0000 THS6 - THS0 8.20 LA_INT2_DURATION (37h) Table 52. 0 LA_INT2_DURATION register D6 D5 D4 D3 D2 D1 D0 Table 53. D6 - D0 LA_INT2_DURATION description Duration value. Default value: 000 0000 The D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized. Duration time steps and maximum values depend on the ODR chosen. 38/42 Doc ID 16917 Rev 1 LSM320HAY30 Package information 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 11. LGA-28: mechanical data and package dimensions mm Dim. Min. A1 A2 A3 D1 E1 N1 L1 L2 P2 T1 T2 M d k h Typ. 0.855 0.2 4.4 7.5 0.3 5.4 1.8 1.2 0.6 0.4 0.1 0.3 0.05 0.1 Max. 1.1 Outline and mechanical data 4.25 7.25 4.55 7.55 LGA-28L (4.4x7.5x1.1mm) Land Grid Array Package Pin 1 Indicator hC = k E1 k L1 = C d N1 A A3 D P2 kE D1 E kD A2 Seating Plane A1 T2 K M L2 T1 B TOP VIEW 8190050A Doc ID 16917 Rev 1 39/42 Ordering information LSM320HAY30 10 Ordering information Table 54. Device summary Order code Temperature. range [C] LSM320HAY30 -40 to +85 LSM320HAY30TR Package [mm] LGA-28 (4.4x7.5x1.1) Packing Tray Tape and reel 40/42 Doc ID 16917 Rev 1 LSM320HAY30 Revision history 11 Revision history Table 55. Date 16-Dec-09 14 Document revision history Revision 1 First issue. Changes Doc ID 16917 Rev 1 41/42 LSM320HAY30 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 42/42 Doc ID 16917 Rev 1 |
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